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features ? industry-standard architecture ? emulates many 20-pin pals ? low-cost easy-to-use software tools high-speed electrically-erasab le programmable logic devices ? 12 ns maximum pin-to-pin delay low-power - 5 a (typ) standby current cmos and ttl compatible inputs and outputs ? input and i/o pin keeper circuits advanced flash technology ? reprogrammable ? 100% tested high-reliability cmos process ? 20 year data retention ? 100 erase/write cycles ? 2,000v esd protection ? 200 ma latchup immunity commercial and industrial temperature ranges dual-in-line and surface mount pa ckages in standard pinouts pci-compliant green (pb/halide-free/rohs compli ant) package options available 1. description the atf16v8cz is a high-performance eecmos programmable logic device that uti- lizes atmel?s proven electric ally-erasable flash memory technology. speeds down to 12 ns and a 5 a (typ) edge-sensing power-down mode are offered. all speed ranges are specified over the full 5v 10% range for industrial temperature ranges; 5v 5% for commercial range 5-volt devices. the atf16v8cz incorporates a superset of the generic architectures, which allows direct replacement of the 16r8 family and most 20-pin combinatorial plds. eight out- puts are each allocated eight product terms. three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized. the atf16v8cz can significantly reduce total system power, thereby enhancing sys- tem reliability and reducing power supply costs. when all the inputs and internal nodes are not switching, supply current drops to less than 5 a typically. this auto- matic power-down feature (or sleep mode) allows for power savings in slow clock systems and asynchronous applic ations. also, the pin-keeper circuits eliminate the need for internal pull-up resistors along with their attendant power consumption. high- performance ee pld atf16v8cz 0453h?pld?7/05
2 0453h?pld?7/05 atf16v8cz figure 1-1. block diagram 2. pin configuration and pinouts figure 2-1. tssop figure 2-2. dip/soic table 2-1. pinouts - all pinouts top view pin name function clk clock i logic inputs i/o bi-directional buffers oe output enable vcc +5v supply 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 i/clk i1 i2 i3 i4 i5 i6 i7 i8 gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i9/oe 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 i/clk i1 i2 i3 i4 i5 i6 i7 i8 gnd vcc i/o i/o i/o i/o i/o i/o i/o i/o i9/oe
3 0453h?pld?7/05 atf16v8cz figure 2-3. plcc 4 5 6 7 8 18 17 16 15 14 i3 i4 i5 i6 i7 i/o i/o i/o i/o i/o 3 2 1 20 19 9 10 11 12 13 i8 gnd i9/oe i/o i/o i2 i1 i/clk vcc i/o 3. absolute maximum ratings* temperature under bias.................................. -40c to +85c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: 1. minimum voltage is -0.6v dc, which may under- shoot to -2.0v for pulses of less than 20 ns. maximum output pin voltage is v cc +0.75vdc, which may overshoot to 7.0v for pulses of less than 20 ns. storage temperature ..................................... -65c to +150c voltage on any pin with respect to ground .........................................-2.0v to +7.0v (1) voltage on input pins with respect to ground during programming.....................................-2.0v to +14.0v (1) programming voltage with respect to ground .......................................-2.0v to +14.0v (1) 4. dc and ac operating conditions commercial industrial operating temperature (ambient) 0c - 70c -40c - 85c v cc power supply 5v 5% 5v 10% 4.1 dc characteristics symbol parameter condition min typ max units i il input or i/o low leakage current 0 v in v il (max) -10 a i ih input or i/o high leakage current 3.5 v in v cc 10 a i cc1 power supply current 15 mhz, v cc = max, v in = 0, v cc , outputs open com 95 ma ind. 105 ma i cc (1) power supply current, standby mode 0 mhz, v cc = max, v in = 0, v cc , outputs open com. 5 a ind 5 a i os output short circuit current v out = 0.5v; v cc = 5v; ta = 25c -150 ma v il input low voltage min < v cc < max -0.5 0.8 v v ih input high voltage 2.0 v cc +1 v v ol output low voltage v cc = min, all outputs i ol = -16 ma com, ind. 0.5 v
4 0453h?pld?7/05 atf16v8cz note: 1. all i cc parameters measured with outputs open. data is bas ed on atmel test patterns. reading may vary with pattern. v oh output high voltage v cc = min i ol = -3.2 ma 2.4 v i ol output low current v cc = min com. 24 ma ind. 12 i oh output high current v cc = min com., ind. 4 ma 4.1 dc characteristics symbol parameter condition min typ max units
5 0453h?pld?7/05 atf16v8cz 4.2 ac waveforms (1) note: 1. timing measurement reference is 1.5v. input ac driv ing levels are 0.0v and 3.0v , unless otherwise specified. 4.3 ac characteristics symbol parameter -12 -15 units min max min max t pd input or feedback to non-registered output 3 12 3 15 ns t cf clock to feedback 6 8 ns t co clock to output 2 8 2 10 ns t s input or feedback setup time 10 12 ns t h input hold time 0 0 ns t p clock period 12 16 ns t w clock width 6 8 ns f max external feedback 1/(t s + t co )5545mhz internal feedback 1/(t s + t cf )6250mhz no feedback 1/(t p )8362mhz t ea input to output enable ? product term 3 12 3 15 ns t er input to output disable ? product term 2 15 2 15 ns t pzx oe pin to output enable 2 12 2 15 ns t pxz oe pin to output disable 1.5 12 1.5 15 ns
6 0453h?pld?7/05 atf16v8cz 4.4 input test waveforms 4.4.1 input test waveforms and measurement levels t r , t f < 1.5 ns (10% to 90%) 4.4.2 output test loads note: similar devices are tested with s lightly different loads. these l oad differences may affect output signals' delay and slew rate. atmel devices are test ed with sufficient margins to meet compatible devices. 4.4.3 pin capacitance note: 1. typical values for nominal supply voltage. this parameter is only sampled and is not 100% tested. table 4-1. pin capacitance (f = 1 mhz, t = 25 c (1) ) typ max units conditions c in 58 pf v in = 0v c out 68 pf v out = 0v
7 0453h?pld?7/05 atf16v8cz 4.5 power-up reset the atf16v8cz?s registers are designed to reset during power-up. at a point delayed slightly from v cc crossing v rst , all registers will be rese t to the low state. as a result, the registered out- put state will always be high on power-up. this feature is critical for state machine init ialization. however, due to the asynchronous nature of reset and the uncertainty of how v cc actually rises in the system, the following conditions are required: 1. the v cc rise must be monotonic, from below 0.7v, 2. after reset occurs, all input and feedback setup times must be met before driving the clock term high, and 3. the signals from which the clock is derived must remain stable during t pr . 4.6 preload of registered outputs the atf16v8cz?s registers are provided with circuitry to allow loading of each register with either a high or a low. this fe ature will simplify testing since any state can be forced into the reg- isters to control test sequencing . a jedec file with preload is ge nerated when a source file with vectors is compiled. once down loaded, the jedec file preload sequence will be done automati- cally by approved programmers. 5. security fuse usage a single fuse is provided to prevent unauthor ized copying of the atf 16v8cz fuse patterns. once programmed, fuse verify and preload are inhibited. however, the 64-bit user signature remains accessible. the security fuse should be programmed last, as its effect is immediate. parameter description typ max units t pr power-up reset time 600 1,000 ns v rst power-up reset voltage 3.8 4.5 v
8 0453h?pld?7/05 atf16v8cz 6. input and i/o pin-keeper circuits the atf16v8cz contains internal input and i/o pin-keeper circuits. these circuits allow each atf16v8cz pin to hold its previous value even when it is not being driven by an external source or by the device?s output buffer. this helps insu re that all logic array inputs are at known, valid logic levels. this reduces system power by preventing pins from floating to indeterminate levels. by using pin-keeper circuits rather than pull-up resistors, there is no dc current required to hold the pins in either logic state (high or low). these pin-keeper circuits are im plemented as weak feedback inverters, as shown in the input diagram below. these keeper circuits can easily be overdriven by standard ttl- or cmos-com- patible drivers. the typical overdrive current required is 40 a. figure 6-1. input diagram figure 6-2. i/o diagram
9 0453h?pld?7/05 atf16v8cz 7. functional logic diagram description the logic option and functional diagrams describe the atf16v8cz architecture. eight config- urable macrocells can be configured as a registered output, combinatorial i/o, combinatorial output, or dedicated input. the atf16v8cz can be configured in one of three different modes. each mode makes the atf16v8cz look like a different device. most pld compilers can choose the right mode auto- matically. the user can also force the selection by supplying the compiler with a mode selection. the determining factors would be the usage of register versus combinatorial outputs and dedi- cated outputs versus outputs with output enable control. the atf16v8cz universal architecture can be programmed to emulate many 20-pin pal devices. these architectural subsets can be found in each of the configuration modes described in the following pages. the user can download th e listed subset device jedec programming file to the pld programmer, and the atf16v8cz can be configured to act like the chosen device. check with your programmer m anufacturer for this capability. unused product terms are automatically disabled by the compiler to decrease power consump- tion. a security fuse, when programmed, protects the content of the atf16v8cz. eight bytes (64 fuses) of user signature are accessible to the user for purposes such as storing project name, part number, revision, or date. the user signature is accessible regardless of the state of the security fuse. notes: 1. only applicable for version 3.4 or lower. table 7-1. compiler mode selection registered complex simple auto select abel, atmel-abel p16c8r p16v8c p16v8as p16v8 cupl g16v8ms g16v8ma g16v8as g16v8a log/ic gal16v8_r (1) gal16v8_c7 (1) gal16v8_c8 (1) gal16v8 orcad-pld ?registered? ?complex? ?simple? gal16v8a pldesigner p16v8r p16v8c p16v8c p16v8a tango-pld g16v8r g16v8c g16v8as g16v8
10 0453h?pld?7/05 atf16v8cz 8. macrocell configuration software compilers support the three different omc modes as different device types. these device types are listed in the ta ble below. most compilers have the ability to auto matically select the device type, generally based on the register usage and output enable (oe ) usage. register usage on the device forces the software to choo se the registered mode. all combinatorial out- puts with oe controlled by the product term will force the so ftware to choose the complex mode. the software will choose the simple mode only when all outputs are dedicated combinatorial without oe control. the different device types listed in the table can be used to override the automatic device selection by the software. for further details, refer to the compiler software manuals. when using compiler software to configure the devi ce, the user must pay special attention to the following restrictions in each mode. in registered mode pin 1 and pin 11 are permanently configured as clock and output enable, respectively. these pins cannot be configured as dedicated inputs in the registered mode. in complex mode pin 1 and pin 11 become dedicated inputs and use the feedback paths of pin 19 and pin 12 respectively. because of this fe edback path usage, pin 19 and pin 12 do not have the feedback option in this mode. in simple mode all feedback paths of the output pins are routed via the adjacent pins. in doing so, the two inner most pins (pins 15 and 16) will not have the feedback option as these pins are always configured as dedicated combinatorial output. 8.1 atf16v8cz r egistered mode pal device emulation/pal replacement. the registered mode is used if one or more regis- ters are required. each macrocell can be configured as either a registered or combinatorial output or i/o, or as an input. for a registered output or i/o, the output is enabled by the oe pin, and the register is clocked by the clk pin. eight product terms are allocated to the sum term. for a combinatorial output or i/o, the output enable is controlled by a product term, and seven product terms are allocated to the sum term. when the macrocell is configured as an input, the output enable is permanently disabled. any register usage will make the compiler select this mode. the following registered devices can be emulated using this mode: 16r8 16rp8 16r6 16rp6 16r4 16rp4
11 0453h?pld?7/05 atf16v8cz figure 8-1. registered configuration for registered mode (1)(2) notes: 1. pin 1 controls common clk for the registered outputs. pin 11 controls common oe for the registered outputs. pin 1 and pin 11 are permanently configured as clk and oe . 2. the development software configures all the arch itecture control bits and checks for proper pin usage automatically. figure 8-2. combinatorial configurat ion for registered mode (1)(2) notes: 1. pin 1 and pin 11 are permanently configured as clk and oe . 2. the development software configures all the arch itecture control bits and checks for proper pin usage automatically.
12 0453h?pld?7/05 atf16v8cz figure 8-3. registered mode logic diagram
13 0453h?pld?7/05 atf16v8cz 8.2 atf16v8cz complex mode pal device emulation/pal replacement. in the complex mode, combinatorial output and i/o functions are possible. pins 1 and 11 are regular in puts to the array. pins 13 through 18 have pin feedback paths back to the and-array, which makes full i/o capability possible. pins 12 and 19 (outermost macrocells) are output s only. they do not have input capability. in this mode, each macrocell has seven product terms going to the sum term and one product term enabling the output. combinatorial applic ations with an oe requirement will make the comp iler select this mode. the following devices can be emulated using this mode: 16l8 16h8 16p8 figure 8-4. complex mode option 9. atf16v8cz simple mode pal device emulation/pal replacement. in the simple mode, 8 product terms are allocated to the sum term. pins 15 and 16 (center macrocells) are permanently configured as combinato- rial outputs. other macrocells can be either inputs or combinatorial outputs with pin feedback to the and-array. pins 1 and 11 are regular inputs. the compiler selects this mode when all outputs are combinatorial without oe control. the fol- lowing simple pals can be em ulated using this mode: 10l8 10h8 10p8 12l6 12h6 12p6 14l4 14h4 14p4 16l2 16h2 16p2
14 0453h?pld?7/05 atf16v8cz figure 9-1. simple mode option 0 1
15 0453h?pld?7/05 atf16v8cz figure 9-2. complex mode logic diagram
16 0453h?pld?7/05 atf16v8cz figure 9-3. simple mode logic diagram
17 0453h?pld?7/05 atf16v8cz 9.1 test characterization data
18 0453h?pld?7/05 atf16v8cz
19 0453h?pld?7/05 atf16v8cz
20 0453h?pld?7/05 atf16v8cz 10. ordering information note: shaded parts are being obsoleted in q3-05 and being replaced by green parts. 10.2 using ?c? product for industrial to use commercial product for industrial temperature ranges, down-grade one speed grade from the ?i? to the ?c? device (7 ns ?c? = 10 ns ?i?) and de-rate power by 30%. 10.1 standard package options t pd (ns) t s (ns) t co (ns) ordering code package operation range 12 10 8 atf16v8cz-12jc atf16v8cz-12pc atf16v8cz-12sc atf16v8cz-12xc 20j 20p3 20s 20x commercial (0 c to 70 c) 15 12 10 atf16v8cz-15jc atf16v8cz-15pc 20j 20p3 20s 20x commercial (0 c to 70 c) atf16v8cz-15sc atf16v8cz-15xc 12 10 atf16v8cz-15ji atf16v8cz-15pi 20j 20p3 20s 20x industrial (-40 c to 85 c) atf16v8cz-15si atf16v8cz-15xi 10.3 green package options (pb/halide-fr ee/rohs compliant) t pd (ns) t s (ns) t co (ns) ordering code package operation range 15 12 10 atf16v8cz-15ju atf16v8cz-15pu atf16v8cz-15su atf16v8cz-15xu 20j 20p3 20s 20x industrial (-40 c to 85 c) package type 20j 20-lead, plastic j-leaded chip carrier (plcc) 20p3 20-lead, 0.300" wide, plastic dual inline package (pdip) 20s 20-lead, 0.300" wide, plastic gull-wing small outline (soic) 20x 20-lead, 4.4 mm wide, plastic th in shrink small outline (tssop)
21 0453h?pld?7/05 atf16v8cz 11. package information 11.1 20j ? plcc 2325 orchard parkway san jose, ca 95131 r title drawing no. rev. notes: 1. this package conforms to jedec reference ms-018, variation aa. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 4.191 ? 4.572 a1 2.286 ? 3.048 a2 0.508 ? ? d 9.779 ? 10.033 d1 8.890 ? 9.042 note 2 e 9.779 ? 10.033 e1 8.890 ? 9.042 note 2 d2/e2 7.366 ? 8.382 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ common dimensions (unit of measure = mm) symbol min nom max note 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 d2/e2 b e e1 e d1 d 20j , 20-lead, plastic j-leaded chip carrier (plcc) b 20j 10/04/01
22 0453h?pld?7/05 atf16v8cz 11.2 20p3 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20p3 , 20-lead (0.300"/7.62 mm wide) plastic dual inline package (pdip) d 20p3 1/23/04 pin 1 e1 a1 b e b1 c l seating plane a d e eb ec common dimensions (unit of measure = mm) symbol min nom max note a ? ? 5.334 a1 0.381 ? ? d 24.892 ? 26.924 note 2 e 7.620 ? 8.255 e1 6.096 ? 7.112 note 2 b 0.356 ? 0.559 b1 1.270 ? 1.551 l 2.921 ? 3.810 c 0.203 ? 0.356 eb ? ? 10.922 ec 0.000 ? 1.524 e 2.540 typ notes: 1. this package conforms to jedec reference ms-001, variation ad. 2. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
23 0453h?pld?7/05 atf16v8cz 11.3 20s ? soic 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20s , 20-lead, 0.300" body, plastic gull wing small outline (soic) b 20s 10/23/03 7.60 (0.2992) 7.40 (0.2914) 0.51(0.020) 0.33(0.013) 10.65 (0.419) 10.00 (0.394) pin 1 id 1.27 (0.050) bsc 13.00 (0.5118) 12.60 (0.4961) 0.30(0.0118) 0.10 (0.0040) 2.65 (0.1043) 2.35 (0.0926) 0o ~ 8o 1.27 (0.050) 0.40 (0.016) 0.32 (0.0125) 0.23 (0.0091) pin 1 dimensions in millimeters and (inches). controlling dimension: inches. jedec standard ms-013
24 0453h?pld?7/05 atf16v8cz 11.4 20x ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 20x , (formerly 20t), 20-lead, 4.4 mm body width, plastic thin shrink small outline package (tssop) c 20x 10/23/03 6.60 (.260) 6.40 (.252) 1.20 (0.047) max 0.65 (.0256) bsc 0.20 (0.008) 0.09 (0.004) 0.15 (0.006) 0.05 (0.002) index mark 6.50 (0.256) 6.25 (0.246) seating plane 4.50 (0.177) 4.30 (0.169) pin 1 0.75 (0.030) 0.45 (0.018) 0o ~ 8o 0.30 (0.012) 0.19 (0.007) dimensions in millimeters and (inches). controlling dimension: millimeters. jedec standard mo-153 ac
25 0453h?pld?7/05 atf16v8cz 12. revision history 12.1 0453h 1. green package options added in 2005.
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